This invention relates to a method of making a TFT array for a liquid crystal display (LCD) or image sensor having an increased pixel aperture ratio. More particularly, this invention relates to a method of making an array of TFTs wherein a photo-imageable insulating layer having a plurality of contact vias or apertures disposed therein is located between the address lines and pixel electrodes so that the pixel electrodes are permitted to overlap the row and column address lines without exposing the system to capacitive cross-talk.
Electronic matrix arrays find considerable application in X-ray image sensors and active matrix liquid crystal displays (AMLCDs). Such devices generally include X and Y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in many instances are liquid crystal display pixels or alternatively the memory cells or pixels of an electronically adjustable memory array or X-ray sensor array.
Typically, a switching or isolation device such as a diode or thin film transistor (TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the TFTs act as switching elements for energizing or otherwise addressing corresponding pixel electrodes.
Amorphous silicon (a-Si) TFTs have found wide usage for isolation devices in liquid crystal display (LCD) arrays. Structurally, TFTs generally include substantially co-planar source and drain electrodes, a thin film semiconductor material (e.g. a-Si) disposed between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. Current flow through the TFT between the source and drain is controlled by the application of voltage to the gate electrode. The voltage to the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which current is conducted. Thus, by controlling the voltage to the gate and drain electrodes, the pixels of an AMLCD may be switched on and off in a known manner.
Typically, pixel aperture ratios (i.e. pixel openings) in non-overlapping AMLCDs are only about 50% or less. As a result, either display luminance is limited or backlight power consumption is excessive, thereby precluding or limiting use in certain applications. Thus, it is known in the art that it is desirable to increase the pixel aperture ratio or pixel opening size of LCDs to as high a value as possible so as to circumvent these problems. The higher the pixel aperture ratio (or pixel opening size) of a display, for example, the higher the display transmission. Thus, by increasing the pixel aperture ratio of a display, transmission may be increased using the same backlight power, or alternatively, the backlight power consumption may be reduced while maintaining the same display luminance.
It is known to overlap pixel electrodes over address lines in order to increase the pixel aperture ratio. For example, xe2x80x9cHigh-Aperture TFT Array Structuresxe2x80x9d by K. Suzuki discusses an LCD having an ITO shield plane configuration having a pixel aperture ratio of 40% and pixel electrodes which overlap signal bus lines. An ITO pattern in Suzuki located between the pixel electrodes and the signal lines functions as a ground plane so as to reduce coupling capacitance between the signal lines and the pixel electrode. Unfortunately, it is not always desirable to have a shield electrode disposed along the length of the signal lines as in Suzuki due to production and cost considerations. The disposition of the shield layer as described by Suzuki requires extra processing steps and thus presents yield problems. Accordingly, there exists a need in the art for a LCD with an increased pixel aperture ratio which does not require an ITO shield plane structure to be disposed between the signal lines and pixel electrode.
It is old and well-known to make TFT arrays for LCDs wherein address lines and overlapping pixel electrodes are insulated from one another by an insulating layer. For example, see U.S. Pat. Nos. 5,055,899; 5,182,620; 5,414,547; 5,426,523; 5,446,562; 5,453,857; and 5,457,553.
U.S. Pat. No. 5,182,620 discloses an AMLCD including pixel electrodes which at least partially overlay the address lines and additional capacitor lines thereby achieving a larger numerical aperture for the display. The pixel electrodes are insulated from the address lines which they overlap by an insulating layer formed of silicon oxide or silicon nitride. Unfortunately, the method of making this display as well as the resulting structure are less than desirable because: (i) chemical vapor deposition (CVD) is required to deposit the silicon oxide or silicon nitride insulating film; and (ii) silicon oxide and silicon nitride are not photo-imageable (i.e. contact holes or vias must be formed in such insulating layers by way of etching). As a result of these two problems, the manufacturing process is both expensive and requires more steps than would be otherwise desirable. For example, in order to etch the contact holes in an insulating layer, an additional photo-resist coating step is required and the user must be concerned about layers underneath the insulating layer during etching. With respect to CVD, this is a deposition process requiring expensive equipment.
U.S. Pat. No. 5,453,857 discloses an AMLCD having a TFT array with pixel electrodes formed in an overlapping relation with source signal lines through an insulating thin film. The insulating thin film formed between the signal lines and the pixel electrodes is made of either SiNx, SiO2, TaOx or Al2O3. Unfortunately, the method of making the array and resulting display of the ""857 patent suffers from the same problems discussed above with respect to the ""620 patent. None of the possible insulating layer materials are photo-imageable and etching is required.
U.S. Pat. No. 5,055,899 discloses a TFT array including an insulating film disposed between the address lines and pixel electrodes. Again, etching is required to form the vias in the insulating film. This is undesirable.
U.S. Pat. No. 5,426,523 discloses an LCD including overlapping pixel electrodes and source bus lines, with a silicon oxide insulating film disposed therebetween. Silicon oxide is not photo-imageable and thus necessitates a prolonged and more difficult manufacturing process for the TFT array and resulting AMLCD.
It is apparent from the above that there exists a need in the art for an improved method for manufacturing a TFT array and/or resulting LCD having an increased pixel aperture ratio and little capacitive cross-talk. The method of manufacture, which is improved relative to the prior art, should include forming a photo-imageable insulating layer between pixel electrodes and overlapped bus lines and the vias therein by way of photo-imaging as opposed to resist coating, exposure and developing, and wet or dry etching. The method should be simpler, cheaper, and more efficient to carry out.
It is a purpose of this invention to fulfill the above-described needs in the art, as well as other needs which will become apparent to the skilled artisan from the following detailed description of this invention.
Generally speaking, this invention fulfills the above-described needs in the art by providing a method of making an array of a-Si semiconductor based thin film transitors (TFTs), the method comprising the steps of:
providing a first substantially transparent substrate;
forming an-array of TFTs and corresponding address lines on the first substrate;
depositing an organic photo-imageable insulating layer over the TFT array and corresponding address lines;
photo-imaging the insulating layer in order to form a first array of vias or contact holes therein; and
forming an array of electrode members on the first substrate over the photo-imaged insulating layer so that the electrode members in the array are in communication with the TFTs through the first array of vias or contact holes.
In certain preferred embodiments, the method includes the step of overlapping the address lines with the electrode members so that the photo-imaged insulating layer is disposed therebetween so as to increase the pixel aperture and reduce cross-talk.
In still further preferred embodiments, the method comprises the steps of: (i) using the TFT array in one of a liquid crystal display and an X-ray image sensor, and (ii) forming the insulating layer so as to include one of photo-imageable Benzocyclobutene (BCB) and 2-Ethoxyethyl acetate.
This invention further fulfills the above-described needs in the art by providing a method of making a liquid crystal display including an array of semiconductor switching elements, the method comprising the steps of:
a) providing a first substrate;
b) providing an array of semiconductor based switching elements and corresponding address lines on the first substrate;
c) spin coating an organic photo-imageable insulating layer on the first substrate over the switching elements and address lines;
d) photo-imaging the insulating layer in order to form a first group of vias or contact holes therein, each via in the first group corresponding to one of the switching elements; and
e) forming an array of pixel electrodes over the photo-imaged insulating layer so that each pixel electrode communicates with one of the switching elements through one of the vias in the insulating layer.
This invention still further fulfills the above-described needs in the art by providing a method of making a TFT array comprising the steps of:
a) providing a first substantially transparent substrate;
b) forming a plurality of TFT gate electrodes connected to gate lines on the substrate;
c) forming a gate insulating layer over the gate electrodes;
d) forming and patterning a semiconductor layer over each of the gate electrodes in TFT areas;
e) forming TFT source and drain electrodes in each TFT area with a TFT channel defined therebetween, and a plurality of corresponding drain lines, thereby forming an array of TFTs on the first substrate;
f) depositing a photo-imageable insulating layer over a substantial portion of the substrate so as to cover substantial portions of the gate and drain lines and the TFTs in the array;
g) photo-imaging the insulating layer so as to form a plurality of vias or contact holes therein, at least one via corresponding to each TFT in the array;
h) forming a plurality of pixel electrodes over the insulating layer so that each pixel electrode is in communication with the source electrode of a corresponding TFT through one of the vias; and
i) forming the pixel electrodes on the substrate so that each pixel electrode overlaps at least one of the drain and gate lines whereby the pixel electrodes are insulated from the address lines in the overlap areas by the photo-imaged insulating layer.
This invention will now be described with reference to certain embodiments thereof as illustrated in the following drawings.